1. Field
The present invention relates generally to memory systems, and more particularly to delay locked loop (DLL) circuitry for use in memory systems.
2. Background Art
Data transmission speed requirements have dramatically increased over recent years, and will continue to do so for the foreseeable future. To meet these ever increasing data speed requirements, processors and memory devices have increased their performance, and will continue to increase their performance for the foreseeable future. One of the challenges of increasing memory device performance is to be able to increase the speed of transfer between the memory elements (e.g., memory controller and memory device) while maintaining the integrity of the data transfer.
High speed data transfer between the memory elements requires synchronization in order to maintain the integrity of the transfer. Such synchronization can be provided by a clock signal which provides a timing reference signal for the transfer of the data.
In addition to the increasing data speed requirements, system designers also seek to accomplish this increased functionality while occupying less volume and using less power.